Non-volatile storage devices (EEPROMs, EPROMs and FLASH EEPROMs) may be written information in storage areas that are unaccessible by the user.
Such information is normally written in during the device testing procedure by the manufacturer and concerns the history of individual devices.
The information may include, for example, operation speed class, any redundancy used, manufacturing date and batch, and like items of information.
Non-volatile storage devices comprising memory cells are typically set up into a matrix type of architecture. In this type of architecture, rows and columns of cells are configured with lines to interconnect ceils in one row and cells in one column. In some embodiments, it may be convenient to add, to rows driven by the row decoding facility which permits the user memory matrix to be accessed, a few rows of OTP cells in the matrix.
These rows utilize the same circuitry as the user memory matrix for read and write operations and are enabled by appropriate signals through the row decoding facility.
This kind of circuit architecture is conceptually simple and effective, but can create serious reliability problems with electrically erasable non-volatile storage cell devices, in particular with FLASH EEPROMs.
The possibility to electrically erase information written in memory cells allows thousands of write/erase cycles to be carried out. As the result of these extensive write/erase cycles the circuit elements in such devices, and the memory cells especially, are highly stressed and may develop malfunctions.
In facts where the erasing is performed electrically by acting on the source of the memory cell field-effect transistor with the gate clamped to a ground potential of the device, while the drain potential is allowed to float and the source potential is brought up to a value relative to ground which can generate the required electric field to produce a tunneling effect in the source areas, the selection of the potential reference to which the sources of the OTP cells should be connected becomes a critical one.
It is impossible to leave the source side of the OTP cells connected to that of the user memory cells, constituting the matrix virtual ground, because the erase operation would result in the OTP cells being also erased.
Nor is it practical to connect the source side of the OTP cells to the real ground of the device. Such connection is not practical because, during write operations, the drains are raised to a high potential. The OTP cells, having their drains at a high potential and their sources connected to ground, can inadvertently become erased due to the creation of a subthreshold current. This subthreshold current also produces a depletion that impairs the reliability of the user memory cells in the same column.
These problems have led the designers to avoid the inclusion of rows of OTP cells to the cell matrix with user memory cells of the FLASH EEPROM type.